For the PowerPC 64-bit Little Endian (ppc64le) architecture, a fix was introduced in rawmemchr to prevent a non-volatile register from being clobbered. Additionally, optimized strncmp and strcmp implementations for Power10 were restored to address security vulnerabilities. These changes ensure that vector non-volatile registers are no longer used for 32-byte load and comparison operations, enhancing stability and security.

The AArch64 architecture received significant updates focused on the Scalable Matrix Extension (SME) and vector instruction sets. To conform to the AAPCS64 specification, the SME ZA state is now correctly disabled in clone, clone3, setjmp, and sigsetjmp, ensuring predictable behavior. Numerous fixes and optimizations were applied to SVE and AdvSIMD functions, including pow, tanpi, sinh, and tan, which resolved bugs related to predicate logic and improved both stability and performance. Low-level improvements also included correcting CFI directives to ensure accurate call stack information for debuggers.

On the x86 architecture, support was added for detecting upcoming Intel "Nova Lake" and "Wildcat Lake" processors, enabling appropriate performance tuning. A key performance regression in wmemset was also fixed. A typographical error in the function dispatcher had caused it to incorrectly bypass faster AVX2 and AVX512 implementations on capable hardware, leading to an unnecessary fallback to the slower SSE2 version.

A bug in the Name Service Switch (NSS) library was also addressed. The group merge functionality was not correctly handling ERANGE errors, potentially causing incorrect behavior during group lookups. The fix ensures this error condition is now properly managed.