python-myhdl is a Python hardware description and verification language that helps you go from Python to silicon. MyHDL code can be converted to Verilog and VHDL. It can also be used to convert signals, do co-simulation with Verilog, generating test benches with test vectors for VHDL, Verilog and supports viewing waveform by tracing signal changes in a VCD file.

This update has been submitted for testing by shakthimaan.

9 years ago

This update has been pushed to testing

9 years ago

This update has reached 14 days in testing and can be pushed to stable now if the maintainer wishes

9 years ago

This update has been submitted for stable by shakthimaan.

9 years ago

This update has been pushed to stable

9 years ago

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newpackage
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Test Gating
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submitted
9 years ago
in testing
9 years ago
in stable
9 years ago
BZ#710848 Review Request: python-myhdl - A python hardware description and verification language
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